
// Library name: VLSI_PROJECT
// Cell name: pmos_amp
// View name: schematic
T1 (VSS net5 net5 VSS) lpnfet l=10u w=1u nf=1 m=1 par=1 ngcon=1 ad=5.5e-13 \
        as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 plnest=-1 \
        plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 rgatemod=0 \
        rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p panw6=0p \
        panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 sb=5.5e-07 sd=0u \
        dtemp=0
T7 (out net5 VSS VSS) lpnfet l=10u w=1u nf=1 m=1 par=1 ngcon=1 ad=5.5e-13 \
        as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 plnest=-1 \
        plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 rgatemod=0 \
        rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p panw6=0p \
        panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 sb=5.5e-07 sd=0u \
        dtemp=0
T0 (net036 ref VDD VDD) lppfet l=10u w=200n nf=1 m=1 par=1 ngcon=1 \
        ad=1.1e-13 as=1.1e-13 pd=1.5u ps=1.5u nrd=1.1 nrs=1.1 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
T4 (net5 vin\+ net036 VDD) lppfet l=5u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
T5 (net036 vin\- out VDD) lppfet l=5u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
